A Low-Speed BIST Framework for High-Performance Circuit Testing
نویسندگان
چکیده
Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a Design-for-Test methodology such that high performance devices can be tested on relatively low performance testers. In addition, a BIST framework is discussed based on this methodology. Various implementation aspects of this technique are also
منابع مشابه
BIST for Delay-Faults in Digital High-Speed ICs
Testing of high-speed integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a BIST methodology such that high performance devices can be tested on relatively low performance testers. In addition, also a full BIST technique is add...
متن کاملPerformance of Generic and Recursive Pseudo Exhaustive Two-Pattern Generator
The main objective of this research is to design a Built-in self-test (BIST) technique based on pseudo-exhaustive testing. Two pattern test generator is used to provide high fault coverage. To provides fault coverage of detectable combinational faults with minimum number of test patterns than the conventional exhaustive test pattern generation, increases the speed of BIST and may posses minimum...
متن کاملUART design using FIFO ram and LCR circuit with BIST capability at different baud rate
The way integrated technology is growing becomes very difficult to apply circuit testing using Automatic TEST Equipment of complex circuit for this BIST (Built In Self test) is the solution of complex IC. Here we are applying BIST for UART which is considering as a low speed, low cost data exchange between computer and peripherals. Hence this paper shows implementation of UART with BIST capabil...
متن کاملOn Using Twisted-Ring Counters for Test Set Embedding in BIST
We present a novel built-in self-test (BIST) architecture for high-performance circuits. The proposed approach is especially suitable for embedding precomputed test sets for core-based systems since it does not require a structural model of the circuit, either for fault simulation or for test generation. It utilizes a twisted-ring counter (TRC) for test-per-clock BIST and is appropriate for hig...
متن کاملTAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST
In this paper, we present TAO-BIST, a framework for testing register-transfer level (RTL) controller-datapath circuits using built-in self-test (BIST). Conventional BIST techniques at the RTL generally introduce more testability hardware than is necessary, thereby causing unnecessary area, delay and power overheads. They have typically been applied to only application-specific integrated circui...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2000